About looking back at the milestones as DAC-50 approaches

This seems to be the year for milestone events in the EDA industry, though calculations show some of the “anniversary” designations to be premature. Nevertheless, the first big EDA event of the year is the Design and Verification Conference (DVCon), held in San Jose, CA every February. DVCon celebrated its 10th anniversary this year, after a transformation from HDLcon in 2003, which followed the earlier union of the VHDL International User’s Forum and International Verilog HDL Conference. Those predecessor conferences trace their origins back 25 years and 20 years, respectively.

 

After DVCon, EDA marketers quickly turn to preparations for the June Design Automation Conference (DAC), perhaps with a warm-up at Design, Automation, and Test in Europe (DATE) in March. DAC is the big show, however, and this year marks the 50th such event (and its 49th anniversary). Phil Kaufman Award winner Pat Pistilli received the EDA industry’s’ highest honor for his pioneer work in creating DAC, which grew from his amusingly-named Society to Help Avoid Redundant Effort (SHARE) conference in 1964.

Milestones inevitably lead to some reflection, but also provide an opportunity to look forward to what the future will bring. In our 2nd annual EDA Digest Resource Guide, we will be asking EDA companies to share what they see as the biggest challenges facing the industry in the next five years, and how the industry will change to meet those challenges. Will future innovations be able to match the impact of the greatest past developments in EDA, which enabled the advances in electronics that we benefit from today?

To put that question in perspective, I’ve been developing a Top 10 list of the most significant developments in the history of EDA, based on my personal experiences over the course of my career. That doesn’t go back quite as far as Pat Pistilli’s, but I have seen many of the major developments in EDA first hand, going back to when I started as an IC designer at Texas Instruments. (This was a few years after we stopped cutting rubylith, in case you were wondering.)

We will also be conducting a survey of readers, and will publish the results in the EDA Digest Resource guide in time for DAC-50. To get things started, here are the first five EDA breakthroughs on my list, roughly in historical order.

CALMA GRAPHIC DATA STATION

The first of my Top-10 developments in EDA is the Calma Graphic Data Station, or GDS. To this day the semiconductor industry still utilizes the GDS-II data format developed by Calma as the standard for IC design “tapeouts.” When I started at TI, draftsmen created chip layouts manually with pencil and gridded paper. Those drawings then had to be digitized, which amounted to clicking with a pointing device on every vertex of the layout, to create an electronic database of the IC geometries. This would later be converted by software to a pattern generator format for fabricating the photomasks.

Evolving from the editing of digitized drawings to creating the IC layers in CAD from the beginning, Calma led the way in replacing the error-prone manual drafting process with a dedicated computer and software that automated the process. Calma spawned the EDA era for layout design of both ICs and printed circuit boards, which led to the adoption of Apollo and Sun Microsystems workstations, and the creation of companies such as Mentor Graphics.

SPICE

There should be no argument that the Simulation Program with Integrated Circuit Emphasis, or SPICE, is the most ubiquitous and long-lived tool in the history of the EDA industry. Like Calma, SPICE preceded the industry itself. The 40th anniversary of the creation of SPICE at UC Berkeley was celebrated at the Computer History Museum in 2011. Even if you work as a system-level designer, and your view of the chip design is in C++ or some other higher-level language, your end result still relies on a commercial offspring of SPICE for modeling the semiconductor process and developing the logic libraries for synthesis. If you are a PCB designer, you’ve probably used PSPICE to model your circuits before fabrication.

THE LEVEL 28 TRANSISTOR MODEL, AND HSPICE

I expect that many will be surprised by this choice, but it is based on my first-hand experience. When I was at TI they had their own CAD group that created TI-SPICE. The same was true of other Integrated Device Manufacturers (IDMs) such as Motorola, AnalogDevices, and IBM. When I moved on to the GE Research Lab to form a new VLSI design group, we quickly found that Berkeley SPICE was great as a learning tool, but it wasn’t close to industrial strength in accuracy or robustness, frequently resulting in the dreaded “Failure to Converge” message. Public SPICE transistor models were also too primitive for the advanced process we were developing. Meta-Software solved the first problem with HSPICE, but their lesser-known secret sauce was their device modeling lab. With Meta-Software’s process modeling kits for foundries, Level 28 became the de facto industry standard, years before the Berkeley Short-channel IGFET Model (BSIM). Meta-Software deserves credit for enabling the development of the fabless semiconductor industry. Eventually, the industry chose to not be locked into a proprietary model, but Level 28 served as the benchmark that drove BSIM-3 and other public-domain models to industrial quality.

HARDWARE DESCRIPTION LANGUAGES: VERILOG AND VHDL

What SPICE is to transistor-level design, the Verilog and VHDL Hardware Description Languages (HDLs) and their associated simulators became to logic design. Just as there were predecessors to SPICE, there were also logic simulators before Gateway Design Automation created Verilog-XL. VHDL had its origin in the U.S. Department of Defense, and the ‘V’ in its name stands for the DoD’s Very High-Speed Integrated Circuit (VHSIC) program. Verilog and VHDL were often considered competing HDLs, but in 2000 their respective standards organizations, VHDL International (VI) and Open Verilog International (OVI), were merged to form Accellera.

DESIGN COMPILER

Until Synopsys’ Design Compiler created the ability to perform logic synthesis, all IC design was at the transistor level. Design Compiler hid that detail from digital designers by automating the mapping of HDL to pre-constructed libraries of logic cells. Though competitors later came on the scene, the automation of ASIC designs began with Design Compiler. Synopsys, too, recently celebrated a milestone with their 25th anniversary in 2011.

ROUNDING OUT THE LIST

With nearly 50 DACs to showcase developments in the EDA industry, there are a lot to choose from when coming up with a Top 10 list. I believe few, however, have had the impact of the five developments that start out my list. As DVCon shows, design complexity has shifted much of the industry’s focus to verification. Are new developments keeping up with the challenge? I can think of several newer innovations to round out my list. What EDA developments would be on your Top 10 list?

As you ponder that question, here’s a puzzler that may require a bit of detective work: What do Calma, Synopsys and Meta-Software have in common?

Be assured, though, that the answers are out there on the Internet. Send me your answers if you think you know.

Also, be sure to take our survey to contribute to the Top 10 and be entered to win a $100 Visa gift card.

 

 

 

 

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refer to : http://dsp-fpga.com/articles/looking-back-at-the-milestones-as-dac-50-approaches/